The invention relates to a device for dividing a recurrent input signal which alternately comprises first and second edges, a first edge being followed every time by a first interval and a second edge being followed every time by a second interval, said device comprising for division by a non-integer divisor f=N-1/2:
a first connection for the input signal; PA1 a second connection for an output signal; PA1 a counter circuit comprising n dynamic bistable elements, each of which comprises a clock signal input, at least one data signal input, and at least one data signal output, 2.sup.n being larger than 2N-1, at least one of said bistable elements being actuatable by said first edges and at least one data signal output of said bistable elements being coupled to a signal input of at least one other bistable element. PA1 a. two directly successive, equal positions; PA1 b. two mutually equal positions which are spaced apart by an even number of other positions; PA1 c. unique positions which differ from all other positions within the cycle.
Devices of this kind are often used when one or more alternating voltages are to be derived from an alternating voltage signal source and the frequency of the alternating voltage of the signal source is not an integer multiple of at least one of the additional alternating voltages.
This problem inter alia occurs often when data stored in a memory is to be displayed on the display screen of a television receiver. Line and frame synchronization signals (and possibly also other auxiliary signals such as a color subcarrier) must then be derived from a local carrier generator in a synchronization circuit.
Examples of such a display are video games and adaptation circuits (whether built into the receiver or not) for Teletext and/or Viewdata systems.
A device of the described kind is known from U.S. Pat. No. 3,896,387, the FIGS. 3, 5 and 7 of which showing dividers that have divisors equal to 21/2, 31/2 and 31/2, respectively, the number of bistable elements being equal to three. The input signal may be periodic or not. In the known circuit the input signal is inverted in given counter positions. In given circumstances, brief signal pulses are then liable to occur in the circuit which can cause a disturbance; for example, see FIG. 4, lines b, c: FIG. 5, line b; FIG. 8, line b, of the above Patent. The delay transfer times of the signals in the circuit components may influence the shape of such brief pulses and thus may render the circuit susceptible to interference. Furthermore, in the known circuit the output signal is derived directly from the position of a single bistable element. This imposes design restrictions, so that for given divisors solutions are difficult to realize. A "signal input" is to be understood as indicating either a clock signal input or a data signal input.